Start with the document and the engineering problem
US20260065050A1, published on 5 March 2026 with DEEPX Co., Ltd. as applicant, concerns training a neural network and performing inference using heterogeneous processors. A1 identifies a published application, not evidence of a granted patent. This article analyses the published disclosure; it does not establish the current legal status or assert that DX-M1 implements every claimed feature.
Imagine a camera inspecting products on a factory line. A model trained on a powerful development computer must run beside the camera with different memory, supported operations and power constraints. Converting the model may change its accuracy. This factory example is illustrative, not a report of a customer installation or measured performance.
Training and inference serve different purposes
Training adjusts model parameters from examples; inference applies the trained model to a new input. In the example, labelled product images support training, while a newly captured image is classified on the line. The disclosed architecture assigns training to a first processor and inference to a differently configured, more limited second processor.
Deployability is therefore more than copying a file. The target must support the required operations, and the model’s behaviour must be evaluated after conversion. A model that fits the device may still miss defects that the development version detected.
Weights, structure and optimisation
Weights are numerical parameters; structure describes the computational stages and their connections. Changing one is not necessarily changing the other. Pruning removes selected connections or components, while quantisation represents values at reduced precision. These techniques can reduce storage or computation but may affect accuracy, making retraining important.
Figure 5 identifies a training GPGPU (100), inference NPU units (200) and memory (300), with compiler (310), storage (320) and reporting (330) functions. The compiler prepares computation for the target; storage and reporting support the exchange of models and results. These components explain the workflow, rather than prove a particular commercial chip configuration.
Evaluation closes the development loop
The sequence is training, transfer of weights, target inference and evaluation, return of evaluation results, model revision and renewed inference. The training processor uses the feedback to modify the model structure and update weights, then sends the updated weights for execution with the modified model. The target device is not assumed to perform the retraining itself.
Figure 7 separates training data for the GPGPU from test data for the target and shows the feedback path. In the hypothetical factory, known-label test images reveal missed scratches; the development system revises the model and tests it again on the target. The accompanying factory diagram is an explanatory scenario, not experimental evidence.
GPU, NPU and the DX-M1 context
A GPU supports parallel computation; GPGPU refers to using it for general-purpose workloads. An NPU is designed for neural-network operations. The disclosure uses GPGPU training and NPU inference as an example of heterogeneous processing, with compilation adapted to the target’s operations and data representation.
DEEPX presents DX-M1 as an edge AI processor. Edge inference runs near the source of data instead of sending every input to a distant server. It can reduce communication needs, but latency, memory, energy and accuracy depend on the actual system. Product positioning and the scope of a patent application remain separate questions.
What development teams should document
The useful patent-analysis question is how target evaluation affects the next model’s structure and weights, not simply whether two processors are present. Record processor roles, exchanged information, optimisation steps, evaluation conditions and before-and-after model changes. Distinguish changes to the computation graph from parameter updates and subsequent deployment.
IPLEX supports patent analysis and drafting for AI and software systems. A non-confidential system diagram, a description of the technical changes and reproducible evaluation conditions help identify the contribution. The related AI practice and test-time-training analysis provide further context without treating different model-update mechanisms as identical.
Original figure labels are preserved; their technical meaning is explained in the text.
Related analysis: updating weights at test time